The present invention relates to an alignment error measuring mark and a method for manufacturing semiconductor devices using the mark thereof. For more detail, the present invention relates to an improvement of alignment technology for a photolithography process.
In the manufacturing process for semiconductors, processes for etching target films or infusion of impurity are repeated, and a requested semiconductor integrated circuits are manufactured thereby. In the photolithography process thereof, resist films are formed through a coating process for forming a resist film on the wafer surface, an exposure process for drawing one-layer patterns on the resist film thereof, and a developing process for developing exposed films. In the exposure process thereof, a positioning relationship between circuit patterns formed on a substrate (a film under the target film, for example, processed by the above resist pattern) and circuit patterns formed on the target films needs to be controlled precisely. For the above purpose, precisely controlled alignment is done in the exposure process by an alignment error measuring mark.
A general alignment error measuring mark includes a mark formed on a substrate (substrate reference mark) and a mark formed on a resist pattern (resist reference mark). An alignment error of the resist patterns thereof can be detected by measuring a displacement between the substrate reference mark and the resist reference mark, based on the above alignment error measuring mark.
As alignment error measuring marks, the ones described in the following patent documents 1-3 are commonly known, for example.
According to the technology of the patent document 1, the substrate reference mark (referred to as “the first measuring mark 100” in the above patent document) is formed by placing thereof in a shape of rectangular frame (for example, refer to FIG. 1 of the above patent document).
According to the technology of the patent document 2, the substrate reference mark (referred to as “line mark WM” in the above cited document) is formed by placing a plural of line patterns in the directions of X, Y at the given interval (refer to paragraph 0059 and FIG. 2, for example, in the above cited document). Furthermore, according to the technology of the patent document 2, the placement interval of the line patterns thereof is determined so that erosion rarely occurs (refer to paragraph 0047, for example, in the above cited document).
Additionally, according to the technology of the patent document 3, the substrate reference mark is formed by placing a plurality of line patterns in the directions of X, Y at the given interval, wherein the inner half of the line patterns and the outer half thereof are varied with symmetry, step, and line width, etc (refer to paragraph 0036, and FIG. 3, for example, in the above cited document). Furthermore, according to the technology of the patent document 3, the placement interval of the line patterns thereof is determined so that erosion rarely occurs (refer to paragraph 0055, for example, in the above cited document), as well as the technology of the patent document 2.
According to the technologies of the patent documents 1-3, the alignment errors are detected by measuring optically positions of the substrate reference mark and the resist reference mark at the same time (refer to FIG. 2 and paragraphs 0024-0026, for example, in the above cited document).
At the same time, in the photolithography process (process for forming the wiring pattern on the substrate), the substrate reference mark and the resist reference mark can not be measured simultaneously. The reason is that the film being processed is made of metal material and the transparency thereof is poor. Consequently, in the metal photolithography process, an alignment error measuring mark referred to as “box-in box type” is used to form a step of the film processed therein on the step of the substrate reference mark.
FIG. 11 is a schematic diagram showing a structure of the step measuring mark used in the conventional metal photolithography process, and the diagram (A) is a top-view diagram and the diagram (B) is a cross section diagram. As shown in the FIG. 11(B), the inter layer film 1102 is deposited on the semiconductor wafer 1101. Furthermore, the contact hole for multi-wiring (not shown in the diagram) is formed in the above inter layer film 1102, and the hole 1103 for the alignment error measuring mark is formed at the same time. Additionally, in the contact hole and the hole 1103 the conductive material of the plug (Tungsten in the case thereof) 1104 is built in. At the above time point, on the upper surface of the hole 1103, the concavity is formed as the substrate reference mark 1105. Then, the conductive material for forming a wiring pattern (Alminum in the case thereof) 1106 is deposited by sputtering, etc. on the whole surface of the interlayer film. Simultaneously, the concavity 1107 of the alminum film 1106 is formed on the substrate reference mark 1105. Additionally, the resist film 1108 is formed on the alminum film 1106. Then the resist pattern (not shown in the diagram thereof) is formed on the resist film 1108 and the resist reference mark is formed 1109 at the same time.
According to the above mentioned configuration, the concavity 1107 of the alminum film 1106 and the resist reference mark 1109 can be measured optically at the same time. Subsequently, the alignment error thereof can be detected.
Patent document 1: Japanese Patent Journal No. H9-74063
Patent document 2: Japanese Patent Journal No. 2004-134473
Patent document 3: Japanese Patent Journal No. 2004-134474